CVE-2026-53354

In the Linux kernel, the following vulnerability has been resolved:

arm64: errata: Mitigate TLBI errata on various Arm CPUs

A number of CPUs developed by Arm suffer from errata whereby a broadcast

TLBI;DSB sequence may complete before the global observation of writes

which are translated by an affected TLB entry.

These errata ONLY affect the completion of memory accesses which have

been translated by an invalidated TLB entry, and these errata DO NOT

affect the actual invalidation of TLB entries. TLB entries are removed

correctly.

This issue has been assigned CVE ID CVE-2025-10263.

To mitigate this issue, Arm recommends that software follows any

affected TLBI;DSB sequence with an additional TLBI;DSB, which will

ensure that all memory write effects affected by the first TLBI have

been globally observed. The additional TLBI can use any operation that

is broadcast to affected CPUs, and the additional DSB can use any option

that is sufficient to complete the additional TLBI.

The ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate

the issue. Enable this workaround for affected CPUs, and update the

silicon errata documentation accordingly.

Note that due to the manner in which Arm develops IP and tracks errata,

some CPUs share a common erratum number.